During the past decade, peripheral component interconnect (PCI) has provided a very successful general purpose input/output (I/O) interconnect standard. PCI is a general purpose I/O interconnect standard that utilizes PCI signaling technology, including a multi-drop, parallel bus implementation. Unfortunately, traditional multi-drop parallel bus technology is approaching its practical performance limits. In fact, the demands of emerging and future computing models will exceed the bandwidth and scalability limits that are inherent in multiple drop, parallel bus implementations.
Accordingly, it is clear that meeting future system performance needs requires I/O bandwidth that can scale with processing and application demands. Alongside these increasing performance demands, the enterprise server and communication markets require improved scalability, security and quality of service guarantees. Fortunately, technology advances and high speed point-to-point interconnects are enabling system designers to break away from the bandwidth limitations of multiple drop, parallel buses. To this end, system designers have discovered a high-performance, third generation I/O (3GIO) interconnect that will serve as a general purpose I/O interconnect for a wide variety of future computing and communications platforms.
3GIO comprehends the many I/O requirements presented across the spectrum of computing and communications platforms and rolls them into a common scalable and extensible I/O industry specification. One implementation of 3GIO includes a basic physical layer consisting of a differential transmit pair and a differential receiver pair. As such, dual simplex data on these point-to-point connections is self-clocked and its bandwidth increases linearly with interconnect width and frequency. In addition, a message space is provided within the bus protocol that is used to implement legacy side band signals. As a result, a further reduction of signal pins produces a very low pin count connection for components and adapters.
Along with the technological advances provided by 3GIO interconnects, many PC computers are now moving toward including wireless connectivity, such as wireless connectivity via, for example, wireless local area networks (WLAN), Bluetooth™ networks and even Internet access via the Wireless Worldwide Web (or WWAN). Unfortunately, including a 3GIO interconnect within a PC computer supporting wireless connectivity may lead to interference between the various wireless protocols and the 3GIO signal. Therefore, there remains a need to overcome one or more of the limitations in the above-described, existing art.